A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
نویسندگان
چکیده
This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84 V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design. key words: double-edge-triggered, flip-flop, level-converting, sense amplifier, mixed threshold voltage
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 96-C شماره
صفحات -
تاریخ انتشار 2013